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Loop performance
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11	Parallel Computing–248 www.elsevier.com/locate/parco A compiler tool to predict memory hierarchy performance of scientiﬁc codes q B.B. Fraguela a, R. Doallo Add to Reading List Source URL: www.des.udc.es Language: English - Date: 2004-03-17 11:53:46 Cache Compiler optimizations Computer memory Computer architecture Software optimization CPU cache Optimizing compiler Locality of reference Automatic parallelization Infinite loop Memory hierarchy Lookup table
12	Performance Portable Optimizations for Loops Containing Communication Operations Costin Iancu Wei Chen, Katherine Yelick Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-10-24 14:33:15 Compiler optimizations Loop optimization Automatic parallelization Loop nest optimization CPU cache Program optimization Software pipelining Lookup table Distributed computing Fortran Compiler Algorithm
13	Development of Large Scale High Performance Applications with a Parallelizing Compiler B. D I MARTIN O 2 , S. BRIG U G LIO 1 , M. CELIN O 3 , G. F OG ACCIA 1 , G. VLAD 1 , V. ROSATO 3 , M. BRISCOLIN I 4 1 Associazione Eu Add to Reading List Source URL: www.afs.enea.it Language: English - Date: 2008-10-20 10:11:15 Compiler optimizations Parallel computing Concurrent programming languages High Performance Fortran Automatic parallelization Loop optimization Fortran Molecular dynamics Array programming
14	IBM Research - Tokyo Improving the Performance of Trace-based Systems by False Loop Filtering Hiroshige Hayashizaki, Peng Wu#, Add to Reading List Source URL: researcher.watson.ibm.com Language: English* - Date: 2011-09-21 14:37:45 IBM Trace
15	Design of Parallel and High Performance Computing HS 2013 Markus P¨ uschel, Torsten Hoefler Department of Computer Science ETH Zurich Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-11-29 06:51:17 Parallel computing Numerical linear algebra Software optimization Roofline model Software testing Matrix multiplication Multi-core processor FLOPS Loop nest optimization Matrix multiplication algorithm
16	Comparison between QuickThread and OpenMP 3.0 under various system load conditions. Copyright © 2009 QuickThread Programming, LLC www.quickthreadprogramming.com Add to Reading List Source URL: www.quickthreadprogramming.com Language: English - Date: 2012-05-03 14:20:38 Parallel computing Fortran OpenMP Loop optimization Standard Performance Evaluation Corporation
17	OPTIMIZATION AND PERFORMANCE MODELING OF STENCIL COMPUTATIONS ON MODERN MICROPROCESSORS‡ KAUSHIK DATTA†, SHOAIB KAMIL∗†, SAMUEL WILLIAMS∗†, LEONID OLIKER∗, JOHN SHALF∗, KATHERINE YELICK∗† Abstract. St Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:58:43 Computer architecture Cache Central processing unit Microprocessors Computer memory CPU cache Stencil code Loop nest optimization Opteron POWER5 Cell Multi-core processor
18	Multi-Agent Ad Hoc Team Partitioning by Observing and Modeling Single-Agent Performance Etkin Baris Ozgul∗ , Somchaya Liemhetcharat† , and Kian Hsiang Low∗ ∗ Department of Computer Science, National University o Add to Reading List Source URL: somchaya.org Language: English - Date: 2014-12-21 21:40:58 NP-complete problems Partition problem Partition Reinforcement learning Algorithm Agent-based model Multi-agent system Graph partition Loop tiling
19	Microsoft Word - Clear-ComWhitePaper_FSII RF Performance.docx Add to Reading List Source URL: www.clearcom.com Language: English - Date: 2016-03-04 12:51:29 Wireless networking Wireless Technology Computing IEEE 802.11 Multiplexing Software-defined radio Local loop Wi-Fi Frequency-hopping spread spectrum Orthogonal frequency-division multiplexing Direct-sequence spread spectrum
20	Random Acoustic Control Control Methods Control loop Control Performance Dynamic range Add to Reading List Source URL: www.spectraldynamics.com Language: English - Date: 2012-08-03 15:28:08

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